1. Field of the Invention
The present invention relates generally to semiconductor circuits and, more particularly, to a method for making and the resulting structure having high speed interconnect lines that incorporate air-gaps.
2. Description of the Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include metal oxide semiconductor ("MOS") devices having diffused source and drain regions separated by channel regions, and gates located over the channel regions. In practice, an IC chip may include thousands or millions of devices, such as MOS transistors.
One problem with conventional metal interconnect structures is misalignments introduced in the photolithography process. Via holes are typically defined through a dielectric layer with the purpose of forming an "electrical" metal contact between a layer underlying the dielectric layer and a layer overlying the dielectric layer. As circuits become increasingly smaller and dense, interconnect structures between successive patterned metal layers have also become ever more dense. Unfortunately, conventional photolithography techniques are also being pushed to their limit, which has had the effect of introducing misalignments between patterned layers.
FIG. 1A is a cross sectional view of a conventional semiconductor device having a misaligned metal contact 28. The semiconductor device includes a semiconductor substrate 10 having diffusion regions 12 and a polysilicon gate 14 defined between the diffusion regions. A first dielectric layer 19 is deposited over the semiconductor substrate 10, the diffusion regions 12 and the polysilicon gate 14. Via holes are defined through the first dielectric layer 19 down to the polysilicon gate 14 and the diffusion region 12 (i.e., source/drain). The via holes are then conductively filled with tungsten or metal to define conductive contacts 16 and 18. In this example, conductive contacts 16 and 18 are somewhat misaligned, but no significant electrical problem occurred in this case. However, serious misalignments are shown to have occurred in the patterning of a conductive contact 28, which is defined through a second dielectric layer 22.
As can be appreciated, these type of misalignments are becoming ever more prevalent as device feature sizes continue to shrink. As illustrated, the misalignment of conductive contact 28, which is used to interconnect a metal-1 line 24 to a metal-2 line 30, may cause electrical shorts between adjacently patterned features. By way of example, when interconnect density patterns increase, layout "design rules" that are used by designers to determine the closest possible inter-feature spacings are necessarily pushed to their limits. That is, although features are designed to be adequately spaced apart to avoid electrical shorts between features, misalignments (which are unavoidable in dense photolithography patterning) will cause features to be laid out in arrangements that seriously violate minimum inter-feature separations dictated the design rules.
It is also known that interconnect speed is dependent on many factors such as metal density, the number of metal levels, interconnect lengths, interconnect geometry, active device characteristics, etc. However, for a given interconnect system, the speed is directly determined by the interconnect resistance, the capacitance and the drive current. From the material aspect, the dominant factor is the permittivity of the dielectric (or insulating material) material used in the interconnect system. The dielectric material surrounds the interconnect lines and contributes to the parasitic capacitance of the interconnect. This parasitic capacitance is directly proportional to the dielectric constant of the insulator. As is well known, a reduction in the dielectric constant results in increased interconnect speed and also lowers the power dissipated in the interconnects (i.e., the different metal layers). This realization has led to substantial activity in the field of low dielectric constant materials for applications in integrated circuits.
The relative dielectric constant of silicon dioxide (the most commonly employed insulator in integrated circuits) is about 4.0. All of the materials currently being researched for applications as low dielectric constant materials have relative dielectric constants in the range of 2.0 to 4.0. The material with the lowest dielectric constant, however, is air, with a relative dielectric constant of 1. Thus the use of air as the dielectric would provide the most benefit. This, of course, has been widely recognized in the industry.
Recently, the use of air-gaps between metal lines has been proposed as a possible solution. See for example an article entitled "USE OF AIR GAP STRUCTURES TO LOWER INTRALEVEL CAPACITANCE" by J.G. Fleming, et al., DUMIC Conference 222D/97/0139 (1997), which defines conventional uses of air-gaps to lower the dielectric constant. This article is incorporated herein by reference. Although the implementation of air-gaps can help in reducing capacitance, the fabrication of conventional air-gaps is not practical for several reasons. One such reason is that the size and location of the formed air-gaps depend on the spacing between adjacent metal interconnect lines. When the spacings grow to a particular width, the air-gaps extend upward (i.e., are formed at a higher level) above the level of the metal lines. During subsequent CMP processing the air-gaps can open up trapping residues and/or forming stringers at subsequent via metal deposition, which can result in yield reductions.
FIG. 1B illustrates a problem that may occur when air-gaps are intentionally fabricated between metal lines and misalignments in the conductive vias occur. For instance, a substrate 50 is shown having metal lines 54 and 56. A dielectric layer 52 is then deposited over the metal lines 54 and 56 such that an air-gap 62 is formed. In this example, the air-gap 62 is shown to have moved above the metal lines 54 and 56, however, the level of the dielectric layer 52 is still thick enough that the air-gap 62 is not exposed due to a chemical mechanical polishing (CMP) operation that is used to planarize the top of dielectric layer 52. Because misalignments in conductive vias 58 and 60 is common, when the via holes are formed through the dielectric layer 52, a path to the air-gap 62 is defined.
As shown in a top view of FIG. 1C, the misalignment of the via holes used to form the conductive vias 58 and 60 can be at different location along the metal lines 54 and 56. It should be noted that when the via holes are defined and the path to the air-gap 62 is made, process gases and other chemicals can get trapped within the air-gap 62. Still further, when a tungsten deposition is performed to fill the via holes, the tungsten deposition, which is a chemical vapor deposition (CVD) operation, can cause tungsten to line the inner walls 64 of the air-gap 62. When this happens, a conductive link can be formed through the tungsten covered air-gap 64 and the conductive vias 58 and 60 may inadvertently be electrically connected (i.e., causing an electrical short). If this occurs, the entire fabricated circuit can fail to operation for its intended purpose, which will therefore cause a significant drop in yield.
Accordingly, in view of the foregoing, there is a need for a method for making high speed interconnect structures that incorporate air-gaps, however, without having the problems associated with conductive via misalignment.